Memory cell arrays in conventional random access memory circuits (RAMs) are generally organized into independently selectable rows and columns. Selected address signals presented to the address terminals of the device are decoded by a row decoder to select a row of the memory cell array to be communicated to sense amplifiers. Others of the address signals are decoded by a column decoder in order to select one or more of the bits in the selected row from or to which data is to be read or written. Such column decoders in conventional RAMs thus in effect perform a multiplexing operation to select one of the many possible bits in a selected row.
Referring to FIG. 1, a common column decoding and demultiplexing scheme is illustrated, realized for the example of a one-of-four selection. Signals A0 and A0.sub.-- are the logical complement of one another, and constitute the least significant bit of the two address signals; similarly signals A1 and A1.sub.-- present the true and false state of the second least significant address bit. AND gates 10.sub.0 through 10.sub.3 are connected to the various combinations of the four true and false address lines, to generate a high logic level at its output responsive to the proper combination of address signals at its inputs. For example, the output of AND gate 10.sub.2 will be high responsive to address lines A0 and A1.sub.-- being high (address 10.sub.2). A high output from an AND gate 10 will turn on the associated pass transistor 12.sub.0 through 12.sub.3, which will connect the corresponding data line D.sub.0 through D.sub.3 to line OUT. Lines D.sub.0 through D.sub.3 are the data lines driven by, for example, four sense amplifiers in a RAM device, among which the circuitry of FIG. 1 is to select for application to line OUT. Alternatively, lines D.sub.0 through D.sub.3 may be the actual bit lines of the memory device, prior to sensing, for such memories which utilize a single sense amplifier for multiple columns. As shown in FIG. 1, transistor 14 is connected between line OUT and the V.sub.dd power supply, to precharge line OUT to V.sub.dd when signal PC at the gate of transistor 14 is high. Line OUT is then either pulled down if the state of the selected data line D.sub.0 through D.sub.3 is low, or left high if the selected data line is high. As is well known in the art, data lines D.sub.0 through D.sub.3 can directly drive (i.e., discharge or keep) line OUT, or may in turn gate a discharge capacitor to discharge line OUT in the event of a logic low thereupon. Many other realizations of the column decoder shown in FIG. 1 may of course be realized using the pass gate concept, including domino logic realizations and other precharge-discharge schemes. In addition, many more pass gates may be used to decode more address lines to select a bit or bits from a group of data lines much larger (e.g., a group of 128) than the four illustrated in FIG. 1.
It is well known that transient gamma radiation exposure of a device containing a circuit such as is shown in FIG. 1 can cause the pass transistors 12, and also the precharge transistor 14, to conduct due to photoconduction, even though the transistors are nominally off. If these transistors conduct in the off state, the state of line OUT could become upset from that of the logic state of the selected data line D.sub.0 through D.sub.3, due to the V.sub.dd power supply driving line OUT toward a high voltage through photoconducting transistor 14, and due to the unselected ones of data lines D.sub.0 through D.sub.3 pulling line OUT through their associated photoconducting pass transistors 12 to their logic level. If the sum of the photoconduction current through transistor 14 and the unselected pass transistors 12 reaches the level of the current through the selected one of pass transistors 12.sub.0 through 12.sub.3, an error can be produced. The worst case of such an event for the circuit of FIG. 1 is if the selected data line, for example line D.sub.0, is at a low logic level and the unselected data lines D.sub.1 through D.sub.3 were at a high logic level. If the sum of the photoconduction current through the four "off" transistors 14 and 12.sub.1 through 12.sub.3 reaches the level of the current through the selected pass transistor 12.sub.0, the logic low level presented by data line D.sub.0 would not be detected.
It is therefore an object of this invention to provide a column decoder circuitry which is more tolerant of pass transistors conducting in the off state, such as photoconduction occurring in transient radiation events.
It is yet another object of this invention to provide such a column decoder which is constructed in stages, so that a weakened output level from an earlier stage can be boosted by a subsequent stage, further increasing the transient radiation tolerance of the device.
It is yet another object of this invention to provide such a column decoder which has low fan-in and fan-out stages, thereby providing reduced switching-time-to-temperature sensitivity.
Other objects and advantages of the invention will become apparent to those of ordinary skill in the art having reference to the following specification in conjunction with the drawings.